1. Field of the Invention
This invention relates to a semiconductor device and a method for manufacturing the same.
2. Background Art
A technique for three-dimensionally arranging memory cells is proposed in, for instance, JP-A 2007-266143 (Kokai). In this technique, a plurality of conductive layers, each functioning as a word electrode or control gate in a memory device, and insulating layers are alternately stacked into a stacked structure. Through holes (memory holes) are formed in the stacked structure, and a charge storage layer is formed on the inner wall of the hole, in which silicon is subsequently buried in a columnar shape.
Furthermore, in the technique disclosed in JP-A 2007-266143 (Kokai), the end portions of the conductive layers are formed into a staircase shape, and each conductive layer is connected to an upper interconnect in the staircase-shaped portion. In this structure, each contact hole connecting the conductive layer to the upper interconnect has a different depth depending on the depth position of the corresponding conductive layer. Thus, in the case of simultaneously and collectively forming the contact holes, there is concern about process controllability, such as the difficulty of controlling the amount of etching of each contact hole.